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ics9db403d idt tm /ics tm four output differential buffer for pcie and gen 1 and gen 2 ics9db403d rev l 10/07/09 four output differential buffer for pcie gen 1 and gen 2 datasheet 1 description output features the ics9db403 is compatible with the intel db400v2 differential buffer specification. this buffer provides 4 pci-express gen2 clocks. the ics9db403 is driven by a differential output pair from a ck410b+, ck505 or ck509b main clock generator. ? 4 - 0.7v current-mode differential output pairs supports zero delay buffer mode and fanout mode bandwidth programming available 50-100 mhz operation in pll mode 50-400 mhz operation in bypass mode functional block diagram key specifications outputs cycle-cycle jitter < 50ps outputs skew: 50ps phase jitter: pcie gen1 < 86ps peak to peak phase jitter: pcie gen2 < 3.0/3.1ps rms 28-pin ssop/tssop pacakge available in rohs compliant packaging supports commercial (0 to +70c) and industrial (-40 to +85c) temperature ranges features/benefits spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread. supports undriven differential outputs in pd# and src_stop# modes for power management. note: polarities shown for oe_inv = 0. stop logic src_in src_in# dif(6,5,2,1) control logic bypass#/pll s data sclk pd spread compatible pll 4 iref oe(6,5,2,1) 4 m u x -oe(6, 1) 2
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 2 pin configuration polarity inversion pin list table power groups vdd 1 28 vdda src_in 2 27 gnda src_in# 3 26 iref gnd 4 25 oe_inv vdd 5 24 vdd dif_1 6 23 dif_6 dif_1# 7 22 dif_6# oe_1 8 21 oe_6 dif_2 9 20 dif_5 dif_2# 10 19 dif_5# vdd 11 18 vdd bypass#/pll 12 17 high_bw# sclk 13 16 dif_stop# sdata 14 15 pd# oe_inv = 0 ics9db403d (same as ics9db104) vdd 1 28 vdda src_in 2 27 gnda src_in# 3 26 iref gnd 4 25 oe_inv vdd 5 24 vdd dif_1 6 23 dif_6 dif_1# 7 22 dif_6# oe1# 821 oe6# dif_2 9 20 dif_5 dif_2# 10 19 dif_5# vdd 11 18 vdd bypass#/pll 12 17 high_bw# sclk 13 16 dif_stop sdata 14 15 pd oe_inv = 1 ics9db403d (same as ics9db401) 28-pin ssop & tssop 01 8 oe_1 oe1# 15 pd# pd 16 dif_stop# dif_stop 21 oe_6 oe6# pins oe_inv vdd gnd 1 4 src_in/src_in# 5,11,18, 24 4 dif(1,2,5,6) n/a 27 iref 28 27 analog vdd & gnd for pll core description pin number
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 3 pin decription when oe_inv = 0 pin # pin name pin type description 1 vdd pwr power supply, nominal 3.3v 2 src_in in 0.7 v differential src true input 3 src_in# in 0.7 v differential src complementary input 4 gnd pwr ground pin. 5 vdd pwr power supply, nominal 3.3v 6 dif_1 out 0.7v differential true clock output 7 dif_1# out 0.7v differential complementary clock output 8oe_1 in active high input for enabling output 1. 0 = tri-state outputs, 1= enable outputs 9 dif_2 out 0.7v differential true clock output 10 dif_2# out 0.7v differential complementary clock output 11 vdd pwr power supply, nominal 3.3v 12 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 13 sclk in clock pin of smbus circuitry, 5v tolerant. 14 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 15 pd# in asynchronous active low input pin used to power down the device. the internal clocks are disabled and the vco and the crystal osc. (if any) are stopped. 16 dif_stop# in active low input to stop differential output clocks. 17 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 18 vdd pwr power supply, nominal 3.3v 19 dif_5# out 0.7v differential complementary clock output 20 dif_5 out 0.7v differential true clock output 21 oe_6 in active high input for enabling output 6. 0 = tri-state outputs, 1= enable outputs 22 dif_6# out 0.7v differential complementary clock output 23 dif_6 out 0.7v differential true clock output 24 vdd pwr power supply, nominal 3.3v 25 oe_inv in this latched input selects the polarity of the oe pins. 0 = oe pins active high, 1 = oe pins active low (oe#) 26 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to g round in order to establish the appropriate current. 475 ohms is the standard value. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core.
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 4 pin decription when oe_inv = 1 pin # pin name pin type description 1 vdd pwr power supply, nominal 3.3v 2 src_in in 0.7 v differential src true input 3 src_in# in 0.7 v differential src complementary input 4 gnd pwr ground pin. 5 vdd pwr power supply, nominal 3.3v 6 dif_1 out 0.7v differential true clock output 7 dif_1# out 0.7v differential complementary clock output 8oe1# in active low input for enabling dif pair 1. 1 = tri-state outputs, 0 = enable outputs 9 dif_2 out 0.7v differential true clock output 10 dif_2# out 0.7v differential complementary clock output 11 vdd pwr power supply, nominal 3.3v 12 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 13 sclk in clock pin of smbus circuitry, 5v tolerant. 14 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 15 pd in asynchronous active high input pin used to power down the device. the internal clocks are disabled and the vco is stopped. 16 dif_stop in active high input to stop differential output clocks. 17 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 18 vdd pwr power supply, nominal 3.3v 19 dif_5# out 0.7v differential complementary clock output 20 dif_5 out 0.7v differential true clock output 21 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 22 dif_6# out 0.7v differential complementary clock output 23 dif_6 out 0.7v differential true clock output 24 vdd pwr power supply, nominal 3.3v 25 oe_inv in this latched input selects the polarity of the oe pins. 0 = oe pins active high, 1 = oe pins active low (oe#) 26 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core.
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 5 absolute max symbol parameter min max units vdd_a 3.3v core supply voltage 4.6 v vdd_in 3.3v logic supply voltage 4.6 v v il input low voltage gnd-0.5 v v ih input high voltage v dd +0.5v v ts storage temperature -65 150 c commerical operating range 0 70 c industrial operating range -40 85 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v tambient electrical characteristics - clock input parameters t a = tambient for the desired operating range, supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v i hdi f differential inputs (sin g le-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing min centered around differential zero
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 6 electrical characteristics - input/supply/common output parameters t a = tambient for the desired operating range, supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ihse 2 v dd + 0.3 v1 input low voltage v ilse gnd - 0.3 0.8 v 1 input high current i ihse v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 i dd3.3opc full active, c l = full load; commerical tem p ran g e 175 200 ma 1 i dd3.3opi full active, c l = full load; industrial temp ran g e 190 225 ma 1 all diff p airs driven, c-tem p 50 60 ma 1 all differential p airs tri-stated, c-tem p 46ma1 all diff p airs driven, i-tem p 55 65 ma 1 all differential p airs tri-stated, i-tem p 68ma1 i dd3.3opc full active, c l = full load; commerical tem p ran g e 105 125 ma 1 i dd3.3opi full active, c l = full load; industrial temp ran g e 115 150 ma 1 all diff p airs driven, c-tem p 25 30 ma 1 all differential p airs tri-stated, c-tem p 23ma1 all diff p airs driven, i-tem p 30 35 ma 1 all differential p airs tri-stated, i-tem p 34ma1 f ipll pcie mode (bypass#/pll= 1) 50 100.00 110 mhz 1 f ibypass bypass mode ((bypass#/pll= 0) 33 400 mhz 1 pin inductance l p in 7nh1 c in logic inputs, except src_in 1.5 5 pf 1 c insrc_in src_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 -3db p oint in hi g h bw mode 2 3 4 mhz 1 -3db p oint in low bw mode 0.7 1 1.4 mhz 1 pll jitter peaking t jpeak peak pass band gain 1.5 2 db 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation fre q uenc y f modin allowable frequency ( trian g ular modulation ) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif sto p after oe# deassertion 1 3 cycles 1,3 tdrive_src_stop# t drvstp dif output enable after src_sto p # de-assertion 10 ns 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of pd# and src_stop# 5 ns 1 trise t r rise time of pd# and src_stop# 5 ns 2 smbus voltage v max maximum input voltage 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol i pullup 4ma1 sclk/sdata clock/data rise time t rsmb (max vil - 0.15) to ( min vih + 0.15 ) 1000 ns 1 sclk/sdata clock/data fall time t fsmb (min vih + 0.15) to ( max vil - 0.15 ) 300 ns 1 smbus operating fre q uenc y f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 see timin g dia g rams for timin g re q uirements. i dd3.3pdi i dd3.3pdi 9db803 powerdown current single ended inputs, 3.3 v +/-5% input low current i dd3.3pdc 9db803 supply current 9db403 supply current 9db403 powerdown current 5 the differential in p ut clock must be runnin g for the smbus to be active input frequency 4 src_in in p ut i dd3.3pdc 3 time from deassertion until out p uts are >200 mv pll bandwidth bw capacitance
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 7 electrical characteristics - dif 0.7v current mode differential pair t a =tambient; v dd = 3.3 v +/-5%; c l =2pf, r s =33 ? , r p =49.9 ? , r re f =475 ? parameter symbol conditions min typ max units notes current source output impedance zo 1 3000 ? 1 voltage high vhigh 660 850 1,2 voltage low vlow -150 150 1,2 max voltage vovs 1150 1 min volta g e vuds -300 1 crossing voltage (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 t p dbyp bypass mode, v t = 50% 2500 4500 ps 1 t p dpll pll mode v t = 50% -250 250 ps 1 skew, output to output t sk3 v t = 50% 50 ps 1 pll mode 50 ps 1,3 additiv e jitter in b y pass mode 50 ps 1,3 pcie gen1 phase jitter (additive in bypass mode) 710 ps (pk2pk) 1,4,5 pcie gen 2 low band phase jitter (additive in bypass mode) 00.1 ps (rms) 1,4,5 pcie gen 2 high band phase jitter (additive in bypass mode) 0.3 0.5 ps (rms) 1,4,5 pcie gen 1 phase jitter 40 86 ps (pk2pk) 1,4,5 pcie gen 2 low band phase jitter 1.5 3 ps (rms) 1,4,5 pcie gen 2 high band phase jitter 2.7/ 2.2 3.1 ps (rms) 1,4,5,6 1 guaranteed by design and characterization, not 100% tested in production. 2 i re f = v dd / (3xr r ). for r r = 475 ? (1%), i re f = 2.32ma. i oh = 6 x i re f and v oh = 0.7v @ z o =50 ? . 3 measured from differential waveform 4 see http://www.pcisi g .com for complete specs 5 device driven by 932s421c or equivalent. 6 first number is high bandwidth mode, second number is low bandwidth mode statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended si g nal usin g absolute value. mv t jphasebyp jitter, phase t jphasepll skew, input to output jitter, cycle to cycle t jcyc-cyc
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 8 clock periods differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term avera g e long-term avera g e period long-term avera g e short-term avera g e period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2,3 dif 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2,4 dif 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2,4 dif 200 4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2,4 dif 266 3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2,4 dif 333 2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2,4 dif 400 2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2,4 clock periods differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term avera g e long-term avera g e period long-term avera g e short-term avera g e period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2,3 dif 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2,4 dif 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2,4 dif 200 4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2,4 dif 266 3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2,4 dif 333 2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2,4 dif 400 2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2,4 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, pll or bypass mode 4 driven by cpu output of ck410/ck505 main clock, b yp ass mode onl y definition units signal name signal name measurement window symbol 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck409/ck410/ck505 accuracy requirements. the 9db403/803 itself does not contribute to ppm error. notes notes definition measurement window units symbol
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 9 src reference clock common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50 ohm trace. 0.5 max inch 1 l2 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 l3 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1 l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1 differential routing to pci express connector dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 2 figure 1 down device routing. rs rs rt rt hscl output buffer pci ex board down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? figure 1 figure 2 pci express connector routing. rs rs rt rt hscl output buffer pci ex add in board ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? figure 2
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 10 alternative termination for lvds and other common differential signals. figure 3. vdiff vp-p vcm r1 r2 r3 r4 note 0.45 v 0.22v 1.08 33 150 100 100 0.58 0.28 0.3 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 cable connected ac coupled application, figure 4 component value note r5a,r5b 5% r6a,r6b cc 0.1 0.350 vcm volts figure_3. r1b r1a r2a r2b hscl output buffer down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? r3 r4 figure_4. pcie device ref_clk input l4 l4? r6b r5b r6a r5a 3.3 volts cc cc 8.2k 5% uf 1k
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 11 general smbus serial interface information for the ics9db403d how to write: ? controller (host) sends a start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address dd (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 12 smbus table: frequency select register, read/write address (dc/dd) pin # name control function t yp e 0 1 defaul t bit 7 pd_mode pd# drive mode rw driven hi-z 0 bit 6 stop_mode src_stop# drive mode rw driven hi-z 0 bit 5 pd_polarity select pd polarity rw low high 0 bit 4 reserved reserved rw x bit 3 reserved reserved rw x bit 2 pll_bw# select pll bw rw hi g h b w low b w 1 bit 1 bypass# bypass#/pll rw fan-out zdb 1 bit 0 src_div# src divide by 2 select rw x/2 1x 1 smbus table: output control register pin # name control function t yp e 0 1 defaul t bit 7 reserved reserved rw 1 bit 6 dif_6 output enable rw disable enable 1 bit 5 dif_5 output enable rw disable enable 1 bit 4 reserved reserved rw 1 bit 3 reserved reserved rw 1 bit 2 dif_2 output enable rw disable enable 1 bit 1 dif_1 output enable rw disable enable 1 bit 0 reserved reserved rw 1 note: the smbus output enable bit must be '1' and the respective oe pin must be active for the output to run! smbus table: oe pin control register pin # name control function t yp e 0 1 defaul t bit 7 reserved reserved rw 0 bit 6 dif_6 dif_6 stoppable with oe6 rw free-run stoppable 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 dif_1 dif_1 stoppable with oe1 rw free-run stoppable 0 bit 0 reserved reserved rw 0 smbus table: reserved register pin # name control function t yp e 0 1 defaul t bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x reserved reserved reserved reserved reserved reserved reserved reserved reserved b y te 0 - - reserved - reserved - - - reserved - - 9,10 - - b y te 1 - 22,23 19,20 - - b y te 2 - - - - 6,7 22,23 6,7 - b y te 3 reserved reserved reserved reserved reserved reserved reserved reserved
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 13 smbus table: vendor & revision id register pin # name control function t yp e 0 1 defaul t bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 1 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function t yp e 0 1 defaul t bit 7 rw 0 bit 6 rw x bit 5 rw x bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 1 bit 0 rw 1 smbus table: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 b y te 4 - revision id - - - - vendor id - - - - - - - - b y te 5 - - - byte 6 - writing to this register configures how many bytes will be read back. - - - - - - - device id 1 device id 6 device id 7 (msb) device id is 83 hex for 9db803 and 43 hex for 9db403 device id 5 device id 4 device id 3 device id 0 device id 2
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 14 the pd# pin cleanly shuts off all clocks and places the device into a power saving mode. pd# must be asserted before shutting off the input clock or power to insure an orderly shutdown. pd is asynchronous active-low input for both powering down the device and powering up the device. when pd# is asserted, all clocks will be driven high, or tri-stated (depending on the pd# drive mode and output control bits) before the pll is shut down. pd#, power down when pd# is sampled low by two consecutive rising edges of dif#, all dif outputs must be held high, or tri-stated (depending on the pd# drive mode and output control bits) on the next high-low transition of the dif# outputs. when the pd# drive mode bit is set to ?0?, all clock outputs will be held with dif driven high with 2 x i ref and dif# tri-stated. if the pd# drive mode bit is set to ?1?, both dif and dif# are tri-stated. pd# assertion power-up latency is less than 1 ms. this is the time from de-assertion of the pd# pin, or vdd reaching 3.3v, or the time from valid src_in clocks until the time that stable clocks are output from the device (pll locked). if the pd# drive mode bit is se t to ?1?, all the dif outputs must driven to a voltage of >200 mv within 300 us of pd# de-assertion. pd# de-assertion pwrdwn# dif dif# pwrdwn# dif dif# tstable <1ms tdrive_pwrdwn# <300us, >200mv note: polarities in timing diagrams are shown oe_inv = 0. they are similar to oe_inv = 1.
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 15 asserting src_stop# causes all dif outputs to stop after their next transition (if the control register settings allow the outp ut to stop). when the src_stop# drive bit is ?0?, the final state of all stopped dif outputs is dif = high and dif# = low. ther e is no change in output drive current. dif is driven with 6xi ref. dif# is not driven, but pulled low by the termination. when the src_stop# drive bit is ?1?, the final state of all dif output pins is low. both dif and dif# are not driven. src_stop# - assertion all stopped differential outputs resume normal operation in a glitch-free manner. the de-assertion latency to active outputs i s 2-6 dif clock periods, with all dif outputs resuming simultaneously. if the src_stop# drive control bit is ?1? (tri-state), al l stopped dif outputs must be driven high (>200 mv) within 10 ns of de-assertion. src_stop# - de-assertion (transition from '0' to '1') the src_stop# signal is an active-low asynchronous input that cleanly stops and starts the dif outputs. a valid clock must be present on src_in for this input to work properly. the src_stop# signal is de-bounced and must remain stable for two consecutive rising edges of dif# to be recognized as a valid assertion or de-assertion. src_stop# pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop_1 (src_stop = driven, pd = driven) src_stop_2 (src_stop =tristate, pd = driven)
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 16 pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop_4 (src_stop = tristate, pd = tristate) src_stop_3 (src_stop = driven, pd = tristate)
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 17 209 mil ssop min max min max a--2.00--.079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.220.38.009.015 c 0.09 0.25 .0035 .010 d e 7.408.20.291.323 e1 5.00 5.60 .197 .220 e l 0.550.95.022.037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 reference doc.: jedec publication 95, mo-150 0.0256 basic common dimensions in millimeters in inches common dimensions 209 mil ssop d (inch) symbol see variations see variations 0.65 basic 28-pin ssop package dimensions
idt tm /ics tm four output differential buffer for pcie gen 1 and gen 2 ics9db403d rev l 10/07/09 ics9db403d four output differential buffer for pcie for gen 1 and gen 2 18 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c minmaxminmax a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations minmaxminmax 28 9.60 9.80 .378 .386 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0. 252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol 28-pin tssop package dimensions ordering information part / order number marking shipping packaging package temperature 9db403dglf 9db403dglf tubes 28-pin tssop 0 to +70 c 9db403dglft 9db403dglf tape and reel 28-pin tssop 0 to +70 c 9DB403DGILF 9DB403DGILF tubes 28-pin tssop -40 to +85 c 9DB403DGILFt 9DB403DGILF tape and reel 28-pin tssop -40 to +85 c 9db403dflf 9db403dflf tubes 28-pin ssop 0 to +70 c 9db403dflft 9db403dflf tape and reel 28-pin ssop 0 to +70 c 9db403dfilf 9db403dfilf tubes 28-pin ssop -40 to +85 c 9db403dfilft 9db403dfilf tape and reel 28-pin ssop -40 to +85 c "lf" denotes pb-free package, rohs complian t "d" is the revision designator (will not correlate to datasheet revision)
ics9db403d four output differential buffer for pcie gen 1 and gen 2 19 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # a 8/15/2006 1. updated electrical characteristics for final data sheet 2. corrected references to 8 outputs (should be 4) - b 5/22/2007 updated polarit y inversion table. 2 c 1/16/2008 1. corrected smbus table to eliminate non-existant outputs. this effects bytes 1 and 2. 2. changed pwd notation to default in smbus descriptions 11 d 2/29/2008 added input clock specs 6 e 3/18/2008 fixed t y po in input clock parameters 6 f 4/9/2008 updated input clock specs 6 g 8/19/2008 corrected typos on bytes 1 and 2. 11 h 8/26/2008 1. updated electrical characteristics to add propagation delay and phase noise information. 2. corrected smbus to reference pin numbers for 403 instead of 803 device. 3. removed references to oe controls that are not present on 403. 4. added smbus electrical characteristics 5. added foot note about dif input running in order for the smbus interface to work 6. added foot note to byte 1 about functionality of oe bits and oe pins. 7. corrected block diagram with proper oe pins indicated. various i 11/26/2008 updated smbus table - b y te0:b y te3. 11 j 2/6/2009 added industrial temp. specs and ordering information. various k 7/13/2009 updated general description and block diagram 1 l 10/7/2009 1. clarified that vih and vil values were for single ended inputs 2. added separate idd values for the 9db403 3. added differential clock input parameters. various

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